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authorArthur Heymans <arthur@aheymans.xyz>2019-11-12 12:05:38 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-25 09:18:22 +0000
commit1fa240a3c5d2a6e8cd63eff24f227abc3333753b (patch)
tree19b26ef5f947bc4d82461b20ec263d4feabbc1c9 /src/cpu/intel/car
parentdf0c731e688f55caf61fa721d32f1725e241aca5 (diff)
downloadcoreboot-1fa240a3c5d2a6e8cd63eff24f227abc3333753b.tar.xz
cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK
Console is not yet enabled in bootblock. This will be done in a different CL. Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/car')
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 23df701e08..5262b1886d 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -18,14 +18,10 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#if !CONFIG(ROMCC_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
-#else
-#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
-#endif
.global bootblock_pre_c_entry