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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-09 11:41:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 05:32:44 +0000
commit544878b56349a74e8cb7a0e9af899b5f7fc246fc (patch)
tree0a586dcbe6e70c94be6b7d123f43dd7c294dad68 /src/cpu/intel/car
parent5bc641afebda5fd274ba713add4145651d9bc71d (diff)
downloadcoreboot-544878b56349a74e8cb7a0e9af899b5f7fc246fc.tar.xz
arch/x86: Add postcar_frame_common_mtrrs()
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/car')
-rw-r--r--src/cpu/intel/car/romstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index f6b62192f1..624f3ff9b7 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -33,6 +33,8 @@ static void prepare_and_run_postcar(struct postcar_frame *pcf)
fill_postcar_frame(pcf);
+ postcar_frame_common_mtrrs(pcf);
+
run_postcar_phase(pcf);
/* We do not return here. */
}