cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK

Pass timestamps and BIST to romstage using the same signature
as C_ENVIRONMENT_BOOTBLOCK will.

Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 80 insertions, 59 deletions

diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 9a433d6e3c..981b12dc1a 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -22,11 +22,12 @@
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
+.global bootblock_pre_c_entry
+
 .code32
 _cache_as_ram_setup:
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+bootblock_pre_c_entry:
 
 cache_as_ram:
 	post_code(0x20)
@@ -167,22 +168,24 @@ addrsize_set_high:
 	movl	%eax, %cr0
 
 	/* Setup the stack. */
-	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
-	movl	%eax, %esp
-	/* Align the stack 16 bytes */
+	mov	$_car_stack_end, %esp
+
+	/* Need to align stack to 16 bytes at call instruction. Account for
+	the pushes below. */
 	andl	$0xfffffff0, %esp
-	/* Account for pushing the BIST result */
-	subl	$12, %esp
+	subl	$4, %esp
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
-	movl	%esp, %ebp
-	pushl	%eax
+	/* push TSC and BIST to stack */
+	movd	%mm0, %eax
+	pushl	%eax 	/* BIST */
+	movd	%mm2, %eax
+	pushl	%eax	/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax 	/* tsc[31:0] */
 
-before_romstage:
+before_c_entry:
 	post_code(0x29)
-	/* Call romstage.c main function. */
-	call	romstage_main
+	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
 	post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 163f4b4d84..4ac6d29232 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -25,11 +25,12 @@
 
 #define NoEvictMod_MSR 0x2e0
 
+.global bootblock_pre_c_entry
+
 .code32
 _cache_as_ram_setup:
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+bootblock_pre_c_entry:
 
 cache_as_ram:
 	post_code(0x20)
@@ -171,23 +172,24 @@ addrsize_set_high:
 	movl	%eax, %cr0
 
 	/* Setup the stack. */
-	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
-	movl	%eax, %esp
+	mov	$_car_stack_end, %esp
 
-	/* Align the stack 16 bytes */
+	/* Need to align stack to 16 bytes at call instruction. Account for
+	the pushes below. */
 	andl	$0xfffffff0, %esp
-	/* Account for pushing the BIST result */
-	subl	$12, %esp
+	subl	$4, %esp
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
-	movl	%esp, %ebp
-	pushl	%eax
+	/* push TSC and BIST to stack */
+	movd	%mm0, %eax
+	pushl	%eax 	/* BIST */
+	movd	%mm2, %eax
+	pushl	%eax	/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax 	/* tsc[31:0] */
 
-before_romstage:
+before_c_entry:
 	post_code(0x29)
-	/* Call romstage.c main function. */
-	call	romstage_main
+	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
 	post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 121d169daf..280913163a 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -23,11 +23,12 @@
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
+.global bootblock_pre_c_entry
+
 .code32
 _cache_as_ram_setup:
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+bootblock_pre_c_entry:
 
 cache_as_ram:
 	post_code(0x20)
@@ -156,18 +157,24 @@ addrsize_set_high:
 	movl	%eax, %cr0
 
 	/* Setup the stack. */
-	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
-	movl	%eax, %esp
-
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
-	movl	%esp, %ebp
-	pushl	%eax
-
-before_romstage:
-	post_code(0x2f)
-	/* Call romstage.c main function. */
-	call	romstage_main
+	mov	$_car_stack_end, %esp
+
+	/* Need to align stack to 16 bytes at call instruction. Account for
+	the pushes below. */
+	andl	$0xfffffff0, %esp
+	subl	$4, %esp
+
+	/* push TSC and BIST to stack */
+	movd	%mm0, %eax
+	pushl	%eax 	/* BIST */
+	movd	%mm2, %eax
+	pushl	%eax	/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax 	/* tsc[31:0] */
+
+before_c_entry:
+	post_code(0x29)
+	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
 	post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index eb5e4909d5..8587ea522f 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -28,11 +28,12 @@
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
+.global bootblock_pre_c_entry
+
 .code32
 _cache_as_ram_setup:
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+bootblock_pre_c_entry:
 
 cache_as_ram:
 	post_code(0x20)
@@ -353,22 +354,24 @@ skip_cache_rom:
 	movl	%eax, %cr0
 
 	/* Setup the stack. */
-	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
-	movl	%eax, %esp
-	/* Align the stack 16 bytes */
+	mov	$_car_stack_end, %esp
+
+	/* Need to align stack to 16 bytes at call instruction. Account for
+	the pushes below. */
 	andl	$0xfffffff0, %esp
-	/* Account for pushing the BIST result */
-	subl	$12, %esp
+	subl	$4, %esp
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
-	movl	%esp, %ebp
-	pushl	%eax
+	/* push TSC and BIST to stack */
+	movd	%mm0, %eax
+	pushl	%eax 	/* BIST */
+	movd	%mm2, %eax
+	pushl	%eax	/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax 	/* tsc[31:0] */
 
-before_romstage:
+before_c_entry:
 	post_code(0x2f)
-	/* Call romstage.c main function. */
-	call	romstage_main
+	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
 	post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index e21ea467c2..b9d787fdc0 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
@@ -19,7 +20,7 @@
 
 #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
 
-asmlinkage void *romstage_main(unsigned long bist)
+static void romstage_main(unsigned long bist)
 {
 	int i;
 	const int num_guards = 4;
@@ -50,7 +51,12 @@ asmlinkage void *romstage_main(unsigned long bist)
 	}
 
 	platform_enter_postcar();
+}
 
-	/* We do not return. */
-	return NULL;
+/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+	romstage_main(bist);
 }