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authorArthur Heymans <arthur@aheymans.xyz>2018-06-03 17:14:19 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-08-13 15:12:38 +0000
commit348b79f05733d1186ccd3b03a990fa4694885e7e (patch)
tree62deaa7c1f341d8f3b73cc6cd2289c7ee3c6d5ab /src/cpu/intel/car
parent995b99d9963e0ada5ef46d45a50ebefdb9dd090a (diff)
downloadcoreboot-348b79f05733d1186ccd3b03a990fa4694885e7e.tar.xz
cpu/intel/car: Align the stack to 16 bytes before romstage_main
Change-Id: I1415c18779bc481fdec5f72f83c06a58ce6d5c39 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26797 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/car')
-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S5
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S4
3 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index e70454b288..3399510b76 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -169,6 +169,10 @@ addrsize_set_high:
/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
+ /* Align the stack 16 bytes */
+ andl $0xfffffff0, %esp
+ /* Account for pushing the BIST result */
+ subl $12, %esp
/* Restore the BIST result. */
movl %ebp, %eax
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 0768c323f1..8f4cfe7409 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -174,6 +174,11 @@ addrsize_set_high:
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
+ /* Align the stack 16 bytes */
+ andl $0xfffffff0, %esp
+ /* Account for pushing the BIST result */
+ subl $12, %esp
+
/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 95ecba96bd..60423967a5 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -355,6 +355,10 @@ skip_cache_rom:
/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
+ /* Align the stack 16 bytes */
+ andl $0xfffffff0, %esp
+ /* Account for pushing the BIST result */
+ subl $12, %esp
/* Restore the BIST result. */
movl %ebp, %eax