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authorPatrick Georgi <patrick@georgi-clan.de>2011-10-31 17:07:52 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-11-01 19:06:23 +0100
commit784544b934d67dc85ccfcf33e04ff148045836ad (patch)
tree8f120ca06da0b126f09526d8814708b95ea6259f /src/cpu/intel/car
parent36c04e8a5c54b100a505650218419e112ccc266e (diff)
downloadcoreboot-784544b934d67dc85ccfcf33e04ff148045836ad.tar.xz
Remove XIP_ROM_BASE
The base is now calculated automatically, and all mentions of that config option were typical anyway (4GB - XIP_ROM_SIZE). Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/366 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/car')
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 26fec6e594..7742a68225 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -229,7 +229,7 @@ clear_fixed_var_mtrr_out:
simplemask CacheSize, 0
wrmsr
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
/*
* Enable write base caching so we can do execute in place (XIP)
@@ -250,7 +250,7 @@ clear_fixed_var_mtrr_out:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax