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authorArthur Heymans <arthur@aheymans.xyz>2019-02-08 16:27:35 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-10 10:53:29 +0000
commiteeedf83bcddf7003d8a2d69740689febe95f821a (patch)
tree3c5e590f2649a9dd651ee63c03bc1705ffc8e111 /src/cpu/intel/car
parent8da24f156f7f39f914ff9fa7c8e12c74c4cff80a (diff)
downloadcoreboot-eeedf83bcddf7003d8a2d69740689febe95f821a.tar.xz
cpu/intel/car/*/cache_as_ram.S: Add brackets around operand
Change-Id: I644c38c9b8383db25a970dc7a5ec8765980298ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31291 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/car')
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index f32b3dcf47..7788a2da4e 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -118,7 +118,7 @@ addrsize_set_high:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
- movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
+ movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index f84e85565e..9d50582232 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -304,7 +304,7 @@ no_msr_11e:
/* Cache the whole rom to fetch microcode updates */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
- movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
+ movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx