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| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/cpu/intel/car | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel/car')
| -rw-r--r-- | src/cpu/intel/car/non-evict/cache_as_ram.S | 4 | ||||
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 4 | ||||
| -rw-r--r-- | src/cpu/intel/car/romstage.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 7788a2da4e..b2b915fe76 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -134,7 +134,7 @@ addrsize_set_high: orl $MTRR_DEF_TYPE_EN, %eax wrmsr -#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR) +#if CONFIG(CPU_HAS_L2_ENABLE_MSR) /* * Enable the L2 cache. Currently this assumes that this * only affect socketed CPU's for which this is always valid, @@ -152,7 +152,7 @@ addrsize_set_high: invd movl %eax, %cr0 -#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +#if CONFIG(MICROCODE_UPDATE_PRE_RAM) update_microcode: /* put the return address in %esp */ movl $end_microcode_update, %esp diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 9d50582232..4beac0b94c 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,7 +23,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) /* Fixed location, ASSERTED in failover.ld if it changes. */ .set ap_sipi_vector_in_rom, 0xff #endif @@ -318,7 +318,7 @@ no_msr_11e: invd movl %eax, %cr0 -#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +#if CONFIG(MICROCODE_UPDATE_PRE_RAM) update_microcode: /* put the return address in %esp */ movl $end_microcode_update, %esp diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 264ad4ab7f..a7daff4fb2 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -54,7 +54,7 @@ static void romstage_main(unsigned long bist) platform_enter_postcar(); } -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) /* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, * keeping changes in cache_as_ram.S easy to manage. */ |