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authorMartin Roth <gaumless@gmail.com>2014-04-25 15:09:27 -0600
committerMartin Roth <martin.roth@se-eng.com>2014-05-09 21:36:12 +0200
commit2dd3f877cc7926f5ac1cfd5a7e5d546c8be2121c (patch)
tree164e0f702179302236d8477d889804e405f143a2 /src/cpu/intel/fsp_model_206ax/Kconfig
parenta6427161c20bfb8319208dbbd08697a530a3839e (diff)
downloadcoreboot-2dd3f877cc7926f5ac1cfd5a7e5d546c8be2121c.tar.xz
cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/cpu/intel/fsp_model_206ax/Kconfig')
-rw-r--r--src/cpu/intel/fsp_model_206ax/Kconfig23
1 files changed, 1 insertions, 22 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3aacaf79f9..1db5030013 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -28,6 +28,7 @@ if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX
config CPU_SPECIFIC_OPTIONS
def_bool y
+ select PLATFORM_USES_FSP
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
@@ -70,26 +71,4 @@ config MICROCODE_INCLUDE_PATH
default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-config FSP_IMAGE_ID_DWORD0
- hex
- default 0x2D325453 if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_I89XX
- default 0x2D324343 if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
- help
- The FSP Image ID is different for each platform's FSP and can be used to
- verify that the right FSP binary is loaded.
- For the ivybridge/89xx FSP, the Image Id will be "ST2-FSP\0",
- for ivybridge/bd82x6x FSPs, the Image Id will be "CC2-FSP\0",
- This dword holds the first 4 bytes of the string, as
- a hex value.
-
-config FSP_IMAGE_ID_DWORD1
- hex
- default 0x00505346
- help
- For the ivybridge/I89xx FSP, the Image Id will be "ST2-FSP\0",
- for ivybridge/bd82x6x FSPs, the Image Id will be "CC2-FSP\0",
- This dword holds the second 4 bytes of the string, as
- a hex value. Since the strings use the same second dword,
- no additional logic is needed.
-
endif