diff options
| author | zaolin <zaolin.daisuki@gmail.com> | 2018-10-31 16:43:43 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-19 15:43:37 +0000 |
| commit | 3313a78e36da73f05da7402699f04909595a0c9d (patch) | |
| tree | 1dcd09a9df05ec94d15178f929b7ae063fdf7646 /src/cpu/intel/fsp_model_206ax/Kconfig | |
| parent | 0b8aefc6562c64665425617eddd22aec2610bda5 (diff) | |
| download | coreboot-3313a78e36da73f05da7402699f04909595a0c9d.tar.xz | |
northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/fsp_model_206ax/Kconfig')
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/Kconfig | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig deleted file mode 100644 index 878244861c..0000000000 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ /dev/null @@ -1,50 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - - -config CPU_INTEL_FSP_MODEL_206AX - bool - -config CPU_INTEL_FSP_MODEL_306AX - bool - -if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX - -config CPU_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select SSE2 - select UDELAY_LAPIC - select SMM_TSEG - select SUPPORT_CPU_UCODE_IN_CBFS - select PARALLEL_CPU_INIT - select TSC_SYNC_MFENCE - select LAPIC_MONOTONIC_TIMER - select CPU_INTEL_COMMON - -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/fsp_model_206ax/bootblock.c" - -config SMM_TSEG_SIZE - hex - default 0x800000 - -endif |