diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-10-30 09:03:43 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 01:44:40 +0100 |
| commit | 76c3700f02f79b49fec30d6ef18d336f122cbf50 (patch) | |
| tree | cb1c750ef3946e2ae462e1847ec89946579274b2 /src/cpu/intel/haswell/Kconfig | |
| parent | cc86e63e835ab0bceb62215460a13266a791cdd3 (diff) | |
| download | coreboot-76c3700f02f79b49fec30d6ef18d336f122cbf50.tar.xz | |
haswell: Add initial support for Haswell platforms
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
the southbridge support is included as well. The basis for this code is
the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
more attention, but this is a good starting point.
This code partially gets up through the romstage just before training
memory on a Haswell reference board.
Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2616
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/Kconfig')
| -rw-r--r-- | src/cpu/intel/haswell/Kconfig | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig new file mode 100644 index 0000000000..5b24a8bce4 --- /dev/null +++ b/src/cpu/intel/haswell/Kconfig @@ -0,0 +1,33 @@ + +config CPU_INTEL_HASWELL + bool + +if CPU_INTEL_HASWELL + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMP + select SSE2 + select UDELAY_LAPIC + select SMM_TSEG + select CPU_MICROCODE_IN_CBFS + #select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE + +config BOOTBLOCK_CPU_INIT + string + default "cpu/intel/haswell/bootblock.c" + +config SERIAL_CPU_INIT + bool + default n + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config MICROCODE_INCLUDE_PATH + string + default "src/cpu/intel/haswell" + +endif |