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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-12 17:55:49 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-02 16:15:33 +0000 |
| commit | 4f7568b126f8a51f23c994ef7b4acd24a3c64a47 (patch) | |
| tree | 1ed607f0fcc97b00d77bd8e453ca92ad6c388b6a /src/cpu/intel/haswell/bootblock.c | |
| parent | 47be2d9f70c0112da29d560cbef13b6f2bcd5697 (diff) | |
| download | coreboot-4f7568b126f8a51f23c994ef7b4acd24a3c64a47.tar.xz | |
cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
Tested on Thinkpad X200: the romstage execution speeds are back to
pre-C_ENVIRONMENT_BOOTBLOCK levels.
Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/haswell/bootblock.c')
0 files changed, 0 insertions, 0 deletions