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author | Aaron Durbin <adurbin@chromium.org> | 2013-06-13 17:29:36 -0700 |
---|---|---|
committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-01 23:27:10 +0100 |
commit | c7633f4f5e3693c005791006e6cc788b218770c7 (patch) | |
tree | a03a6c4092bbfada0a0c1fbaafb7a3a516a1292e /src/cpu/intel/haswell/haswell.h | |
parent | 752b1e6d5d341e9c328d596a6f00bd8071274a48 (diff) | |
download | coreboot-c7633f4f5e3693c005791006e6cc788b218770c7.tar.xz |
slippy/falco/peppy: Fix SPD GPIO initialization.
SPD GPIOs were being read prior to initialization in romstage_common. To
fix, pass the copy_spd function to romstage_common, to be called at the
appropriate time (after PCH init, before DRAM init).
Change-Id: I2554813e56a58c8c81456f1a53cc8ce9c2030a73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58608
Reviewed-on: http://review.coreboot.org/4237
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
-rw-r--r-- | src/cpu/intel/haswell/haswell.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7dfba863d4..cd007c1f7e 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -151,6 +151,7 @@ struct romstage_params { const void *gpio_map; const struct rcba_config_instruction *rcba_config; unsigned long bist; + void (*copy_spd)(struct pei_data *); }; void mainboard_romstage_entry(unsigned long bist); void romstage_common(const struct romstage_params *params); |