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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 12:37:54 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:59:22 +0000 |
| commit | 88af0f38eb19f956e8df2b62254c10c7603a9a33 (patch) | |
| tree | 97fdbf21a0dca3c0f6c5473e9bf92c0b954df33a /src/cpu/intel/haswell/haswell.h | |
| parent | 02b13fd8cdfbfcb4858ec0e6f66688b96950198e (diff) | |
| download | coreboot-88af0f38eb19f956e8df2b62254c10c7603a9a33.tar.xz | |
cpu/intel/haswell: Switch to POSTCAR_STAGE
Tested on Google Peppy (Acer C720).
Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26793
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 6612509e49..23efe6c443 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -181,9 +181,6 @@ void romstage_common(const struct romstage_params *params); * ... */ asmlinkage void *romstage_main(unsigned long bist); -/* romstage_after_car() is the C function called after cache-as-ram has - * been torn down. It is responsible for loading the ramstage. */ -asmlinkage void romstage_after_car(void); #endif #ifdef __SMM__ |