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| author | Aaron Durbin <adurbin@chromium.org> | 2013-02-15 15:08:37 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 22:58:17 +0100 |
| commit | 67481ddc2e53cd3420fa8c723edb4fe47dccc196 (patch) | |
| tree | 11be0e451c9c208e0e97d63863efb72e88aad59a /src/cpu/intel/haswell/haswell.h | |
| parent | 8584b223fe1a0c9da9a94e28b135cfc7414601dc (diff) | |
| download | coreboot-67481ddc2e53cd3420fa8c723edb4fe47dccc196.tar.xz | |
haswell: set TSEG as WB cacheable in romstage
The TSEG region is accessible until the SMM handler is relocated
to that region. Set the region as cacheable in romstage so that it
can be used for other purposes with fast access.
Change-Id: I92b83896e40bc26a54c2930e05c02492918e0874
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2803
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
0 files changed, 0 insertions, 0 deletions