summaryrefslogtreecommitdiff
path: root/src/cpu/intel/haswell/romstage.c
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-21 21:08:28 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-23 19:09:49 +0200
commitb37d01d3093d45528b1447d792d88f85607595ca (patch)
tree9f0479e4cf998d77ad54a7339769908c6c8d58f1 /src/cpu/intel/haswell/romstage.c
parenta38677b6646fae7284d08fef706a77478c38c547 (diff)
downloadcoreboot-b37d01d3093d45528b1447d792d88f85607595ca.tar.xz
intel/haswell: Add asmlinkage for romstage_after_car()
Change-Id: Ib3c973d2e89d4c25c3bf1e52662fbfcb4b1e4355 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15789 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/haswell/romstage.c')
-rw-r--r--src/cpu/intel/haswell/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 9154316d91..8b15ed546e 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -259,7 +259,7 @@ void romstage_common(const struct romstage_params *params)
}
}
-void romstage_after_car(void)
+void asmlinkage romstage_after_car(void)
{
/* Load the ramstage. */
run_ramstage();