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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-07 12:24:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-09 15:57:52 +0000 |
| commit | ece26961b9fadbec5e7424bd91f10f600430e975 (patch) | |
| tree | 9927e897523fcdfca7f5c127a728d43ac669dc00 /src/cpu/intel/haswell | |
| parent | 394ec02298091e87946a1aa82fba572819410a55 (diff) | |
| download | coreboot-ece26961b9fadbec5e7424bd91f10f600430e975.tar.xz | |
src/cpu: Fix typo
Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/finalize.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index ba2538702e..ce22e629e8 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -72,7 +72,7 @@ void intel_cpu_haswell_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - /* Lock TM interupts - route thermal events to all processors */ + /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); /* Lock memory configuration to protect SMM */ |