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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-20 12:50:20 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 05:39:39 +0200 |
| commit | eb61ea84f7226d6c081441bbb6fbafbb920505db (patch) | |
| tree | 95026f44c1a6830c5d22c6020c4011192f10c612 /src/cpu/intel/haswell | |
| parent | 9ec691429f1d851c08297d65ff56729fccc6397c (diff) | |
| download | coreboot-eb61ea84f7226d6c081441bbb6fbafbb920505db.tar.xz | |
intel car: Unify whitespace and comment fixes
Change-Id: Icd0cc7d27f38bdaee6addb98abec6f310cdd9fae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15759
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 2ccef786fa..3349883c53 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -30,8 +30,7 @@ #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) #define CACHE_MRC_MASK (~CACHE_MRC_BYTES) -#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define NoEvictMod_MSR 0x2e0 @@ -96,7 +95,7 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -108,7 +107,7 @@ clear_mtrrs: andl $~2, %eax wrmsr - /* Clear the cache memory region. This will also fill up the cache */ + /* Clear the cache memory region. This will also fill up the cache. */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi movl $(CACHE_AS_RAM_SIZE >> 2), %ecx @@ -135,8 +134,8 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr |