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authorVladimir Serbinenko <phcoder@gmail.com>2014-01-23 20:37:22 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-01-23 20:51:49 +0100
commit9c70adf26d810405f22ea9f07a10d4f56fee3cb8 (patch)
tree5898a3365699973b87ebca6d1327d097a5cfb8c3 /src/cpu/intel/haswell
parent1287d1cc80c52ff2598f2bae235fc42d8456f44a (diff)
downloadcoreboot-9c70adf26d810405f22ea9f07a10d4f56fee3cb8.tar.xz
intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.
Not used anymore since microcode was moved. Change-Id: Id666c80cb20e90e3664c4dcfcc0c41a4aeb4864c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4788 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell')
-rw-r--r--src/cpu/intel/haswell/Kconfig4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 03c3518b41..25df4d15ce 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -39,10 +39,6 @@ config SMM_RESERVED_SIZE
hex
default 0x100000
-config MICROCODE_INCLUDE_PATH
- string
- default "src/cpu/intel/haswell"
-
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n