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authorAaron Durbin <adurbin@chromium.org>2014-01-30 17:19:46 -0600
committerAaron Durbin <adurbin@google.com>2014-02-15 18:39:29 +0100
commit0f333071ef9151b89de3fcf6dc5c14dba596941a (patch)
tree7a250a88218d16dd9baf7d5b1d9a35baa08c3390 /src/cpu/intel/haswell
parente9aaa71fb1e05c4432d768d87071ef842c536cb4 (diff)
downloadcoreboot-0f333071ef9151b89de3fcf6dc5c14dba596941a.tar.xz
coreboot: infrastructure for different ramstage loaders
There are 2 methods currently available in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset to support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5087 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/intel/haswell')
-rw-r--r--src/cpu/intel/haswell/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 60a1c3a155..9e2766808d 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -309,8 +309,6 @@ void romstage_after_car(void)
prepare_for_resume(handoff);
- vboot_verify_firmware(handoff);
-
/* Load the ramstage. */
copy_and_run();
}