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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 19:15:34 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:28:27 +0200
commit585d1a0e7d0025e459a35b470572bcdbfff4e3c8 (patch)
tree05b159c11a72cbd4bcbf18e67a639177388d78a0 /src/cpu/intel/haswell
parent9071670a84281979709191307dc11f1350f81bd8 (diff)
downloadcoreboot-585d1a0e7d0025e459a35b470572bcdbfff4e3c8.tar.xz
src/cpu: Capitalize ROM and RAM
Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15935 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/intel/haswell')
-rw-r--r--src/cpu/intel/haswell/cache_as_ram.inc2
-rw-r--r--src/cpu/intel/haswell/romstage.c6
-rw-r--r--src/cpu/intel/haswell/stage_cache.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 9cdb176ea4..276b9c3a63 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -145,7 +145,7 @@ clear_mtrrs:
wrmsr
post_code(0x27)
- /* Enable caching for ram init code to run faster */
+ /* Enable caching for RAM init code to run faster */
movl $MTRR_PHYS_BASE(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index a05d570ac8..8b62d43e2b 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -113,8 +113,8 @@ static void *setup_romstage_stack_after_car(void)
num_mtrrs++;
top_of_ram = (uint32_t)cbmem_top();
- /* Cache 8MiB below the top of ram. On haswell systems the top of
- * ram under 4GiB is the start of the TSEG region. It is required to
+ /* Cache 8MiB below the top of RAM. On haswell systems the top of
+ * RAM under 4GiB is the start of the TSEG region. It is required to
* be 8MiB aligned. Set this area as cacheable so it can be used later
* for ramstage before setting up the entire RAM as cacheable. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
@@ -123,7 +123,7 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
num_mtrrs++;
- /* Cache 8MiB at the top of ram. Top of ram on haswell systems
+ /* Cache 8MiB at the top of RAM. Top of RAM on haswell systems
* is where the TSEG region resides. However, it is not restricted
* to SMM mode until SMM has been relocated. By setting the region
* to cacheable it provides faster access when relocating the SMM
diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c
index ee945c772f..009cc09ba6 100644
--- a/src/cpu/intel/haswell/stage_cache.c
+++ b/src/cpu/intel/haswell/stage_cache.c
@@ -20,7 +20,7 @@
void stage_cache_external_region(void **base, size_t *size)
{
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
- * The top of ram is defined to be the TSEG base address. */
+ * The top of RAM is defined to be the TSEG base address. */
*size = RESERVED_SMM_SIZE;
*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
}