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| author | Stefan Reinauer <reinauer@chromium.org> | 2013-03-21 11:51:41 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-22 00:00:09 +0100 |
| commit | 24d1d4b47274eb82893e6726472a991a36fce0aa (patch) | |
| tree | 57126316330f6f9d407f605fa831ce530650f069 /src/cpu/intel/haswell | |
| parent | 55ed3106556a9bcbe36d3389dc5230d4a4ee2a40 (diff) | |
| download | coreboot-24d1d4b47274eb82893e6726472a991a36fce0aa.tar.xz | |
x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/bootblock.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index f9c3ba8d6f..bb065c808d 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -23,7 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/intel/microcode/microcode.c> #include "haswell.h" diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4ece6c2f9c..6164de54ed 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -30,7 +30,6 @@ #include <timestamp.h> #include <arch/io.h> #include <arch/stages.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> #include <cbmem.h> |