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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-20 19:41:17 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 12:56:03 +0000 |
| commit | ef90609cbb4229ccc242f67c48a8e14273bf0aac (patch) | |
| tree | bb1ce9a66ee7a0d0458365f284f15a028689816b /src/cpu/intel/microcode | |
| parent | 183ad06f522b279328acb70dfba52d31f9ff9c91 (diff) | |
| download | coreboot-ef90609cbb4229ccc242f67c48a8e14273bf0aac.tar.xz | |
src: capitalize 'RAM'
Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel/microcode')
| -rw-r--r-- | src/cpu/intel/microcode/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 238aad745d..c7bbecbace 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -4,4 +4,4 @@ config MICROCODE_UPDATE_PRE_RAM default y help Select this option if you want to update the microcode - during the cache as ram setup. + during the cache as RAM setup. |