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| author | Patrick Georgi <patrick@georgi-clan.de> | 2011-10-28 20:28:03 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-10-28 22:17:10 +0200 |
| commit | 1da104647dc2828a6594bdc7b5ae119923dbcffa (patch) | |
| tree | 3e4d1e8acc0e37bf0f5d93c4367d072c1629755b /src/cpu/intel/model_106cx | |
| parent | 0f8590f9ca8026af62efa510a1c717d2d0729e3d (diff) | |
| download | coreboot-1da104647dc2828a6594bdc7b5ae119923dbcffa.tar.xz | |
Get rid of AUTO_XIP_ROM_BASE
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
This works as MTRRs are fully specified by their size and any address
within the range.
Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index da14db22ae..b45599ac1b 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -102,17 +102,12 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if CONFIG_TINY_BOOTBLOCK -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif /* - * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $REAL_XIP_ROM_BASE, %eax + movl copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr |