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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-06 23:14:54 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-01-16 05:34:25 +0100 |
| commit | 2c38f50b4ad8850676a70427bf1e2e9e9aab82a4 (patch) | |
| tree | 68fe15f5e270e69ab9810b12fa2bf61d7ff71585 /src/cpu/intel/model_106cx | |
| parent | b4c39902edbba61827c60a75fe84e748e217b8be (diff) | |
| download | coreboot-2c38f50b4ad8850676a70427bf1e2e9e9aab82a4.tar.xz | |
cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.
The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.
The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.
Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/microcode_blob.c | 15 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/model_106cx_init.c | 18 |
4 files changed, 18 insertions, 17 deletions
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index e26bf1fea5..c438008eec 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -6,6 +6,7 @@ config CPU_INTEL_MODEL_106CX select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select SUPPORT_CPU_UCODE_IN_CBFS config CPU_ADDR_BITS int diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 1f217fe7e3..dbc093d018 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -2,3 +2,4 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c new file mode 100644 index 0000000000..573d41f386 --- /dev/null +++ b/src/cpu/intel/model_106cx/microcode_blob.c @@ -0,0 +1,15 @@ +unsigned microcode_updates_106cx[] = { + #include "microcode-M01106C2217.h" + #include "microcode-M01106CA107.h" + #include "microcode-M04106C2218.h" + #include "microcode-M04106CA107.h" + #include "microcode-M08106C2219.h" + #include "microcode-M08106CA107.h" + #include "microcode-M10106CA107.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e0aa120768..0d96172827 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -31,22 +31,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static const uint32_t microcode_updates[] = { - #include "microcode-M01106C2217.h" - #include "microcode-M01106CA107.h" - #include "microcode-M04106C2218.h" - #include "microcode-M04106CA107.h" - #include "microcode-M08106C2219.h" - #include "microcode-M08106CA107.h" - #include "microcode-M10106CA107.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - #define IA32_FEATURE_CONTROL 0x003a #define CPUID_VMX (1 << 5) @@ -135,7 +119,7 @@ static void model_106cx_init(device_t cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); |