diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2011-01-19 06:54:42 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-01-19 06:54:42 +0000 |
| commit | 7b0500c24ca103e8f8d802b476517afc2ac8eef5 (patch) | |
| tree | 9288cd7a3ea130d50e151455ea9c72bf07fd29a2 /src/cpu/intel/model_106cx | |
| parent | 5bb9fd6e4dae32f86a07676228034d3828820037 (diff) | |
| download | coreboot-7b0500c24ca103e8f8d802b476517afc2ac8eef5.tar.xz | |
Revert r5902 to make code more readable again. At least three people like to
have this go away again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 61 |
1 files changed, 46 insertions, 15 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 9b7cad0cf9..d7dba8bf1b 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - save_bist_result() + /* Save the BIST result. */ + movl %eax, %ebp cache_as_ram: post_code(0x20) @@ -66,12 +66,19 @@ clear_mtrrs: xorl %edx, %edx wrmsr - enable_mtrr() + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr - enable_l2_cache() + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -86,7 +93,9 @@ clear_mtrrs: rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - disable_cache() + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -112,7 +121,10 @@ clear_mtrrs: wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -123,8 +135,8 @@ clear_mtrrs: #endif movl %eax, %esp - restore_bist_result() - + /* Restore the BIST result. */ + movl %ebp, %eax movl %esp, %ebp pushl %eax @@ -137,11 +149,18 @@ clear_mtrrs: post_code(0x30) - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 post_code(0x31) - disable_mtrr() + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~(1 << 11)), %eax + wrmsr post_code(0x31) @@ -161,11 +180,17 @@ clear_mtrrs: post_code(0x33) - enable_cache() + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 post_code(0x36) - disable_cache() + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 post_code(0x38) @@ -182,11 +207,17 @@ clear_mtrrs: post_code(0x39) /* And enable cache again after setting MTRRs. */ - enable_cache() + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 post_code(0x3a) - enable_mtrr() + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr post_code(0x3b) |