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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-25 21:43:29 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-25 21:43:29 +0000 |
| commit | e08c29e0e7f1c1e8682bdb66ce0c51d168fdd502 (patch) | |
| tree | cd0596cfcfa193adf76f87f60c71e9960a1d7216 /src/cpu/intel/model_106cx | |
| parent | 5f5436f935412a339e127e0863d39df8a2308830 (diff) | |
| download | coreboot-e08c29e0e7f1c1e8682bdb66ce0c51d168fdd502.tar.xz | |
a single place for the romstage stack for copy_and_run.
geode lx and amd opteron don't use this yet.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index a2c12140a9..767c488d45 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -21,6 +21,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -256,16 +257,7 @@ __main: movl %ebp, %esi - /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run |