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authorStefan Reinauer <reinauer@chromium.org>2012-08-07 14:44:51 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-08-09 00:38:39 +0200
commit0db6820b10c3452764ab62173c3b75cefbf6c215 (patch)
tree95abc6378ed60c37e14de842a7baf014dc60111b /src/cpu/intel/model_106cx
parent4c29d7f27d315ab93c811fb86ba246151dc84da3 (diff)
downloadcoreboot-0db6820b10c3452764ab62173c3b75cefbf6c215.tar.xz
Synchronize rdtsc instructions
The CPU can arbitrarily reorder calls to rdtsc, significantly reducing the precision of timing using the CPUs time stamp counter. Unfortunately the method of synchronizing rdtsc is different on AMD and Intel CPUs. There is a generic method, using the cpuid instruction, but that uses up a lot of registers, and is very slow. Hence, use the correct lfence/mfence instructions (for CPUs that we know support it) Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1422 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel/model_106cx')
-rw-r--r--src/cpu/intel/model_106cx/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index 103ed50d3e..7a75ec1ba3 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -4,9 +4,9 @@ config CPU_INTEL_MODEL_106CX
select SSE2
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT
+ select TSC_SYNC_MFENCE
config CPU_ADDR_BITS
int
default 32
-