diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-09 15:35:30 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-02-09 21:02:35 +0100 |
| commit | 644e83b0070c28ffa0f68ac1966df968b0a500d9 (patch) | |
| tree | 31759c48e465cea9116b618c8c3924f761335874 /src/cpu/intel/model_106cx | |
| parent | dbc6ca7aea6e2474c30b4c3892abe0b3055abf67 (diff) | |
| download | coreboot-644e83b0070c28ffa0f68ac1966df968b0a500d9.tar.xz | |
speedstep: Deduplicate some MSR identifiers
In particular:
MSR_PMG_CST_CONFIG_CONTROL
MSR_PMG_IO_BASE_ADDR
MSR_PMG_IO_CAPTURE_ADDR
Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2337
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/model_106cx_init.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 4bf2924fed..803875d37b 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -80,34 +80,30 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // Lock configuration msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; // TODO Do we want PM1_BASE? Needs SMM? //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); msr.lo = ((PMB0_BASE + 4) & 0xffff); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* set C_LVL controls */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 |