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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-20 08:50:38 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 05:38:38 +0200 |
| commit | a27fba67a0dc8f2d2b991b08dbcd2eb485baa8d7 (patch) | |
| tree | 7baa8a36fc6b32cb94b8a7f8e5757c4ddf55d1e1 /src/cpu/intel/model_106cx | |
| parent | 81527e8d7ff4fc3b0480349b934807bcf4c78c55 (diff) | |
| download | coreboot-a27fba67a0dc8f2d2b991b08dbcd2eb485baa8d7.tar.xz | |
intel model_106cx: Include CAR from socket directory
Since the socket layer is implemented with this CPU model, there
could potentially be multiple CPU models included. There can be
only one cache_as_ram include, so select it directly within
the socket directory.
Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15757
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/Makefile.inc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index d15c362dc0..720052d2b5 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,6 +1,4 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -romstage-y += ../car/romstage.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin |