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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 15:15:05 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-23 14:46:36 +0000 |
| commit | f26693283655eff7c31275621439f8416eeb3242 (patch) | |
| tree | 6c4533fcd186faed76e8805d5fa33b171447f67c /src/cpu/intel/model_106cx | |
| parent | 6336d4c48d2f85629ff668da36711ea794f70ab5 (diff) | |
| download | coreboot-f26693283655eff7c31275621439f8416eeb3242.tar.xz | |
nb/intel/i945: Use parallel MP init
Use the parallel mp init path to initialize AP's. This should result
in a moderate speedup.
Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is
26ms faster compared to lapic_cpu_init.
This removes the option to disable HT siblings.
Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/model_106cx_init.c | 12 |
2 files changed, 9 insertions, 4 deletions
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 0703099097..eec544d79a 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -2,5 +2,6 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name subdirs-y += ../common subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index a609aed550..24a9ad29f6 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -85,15 +85,18 @@ static void model_106cx_init(struct device *cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode_from_cbfs(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) { + x86_setup_mtrrs(); + x86_mtrr_check(); + } /* Enable the local CPU APICs */ setup_lapic(); @@ -110,7 +113,8 @@ static void model_106cx_init(struct device *cpu) /* TODO: PIC thermal sensor control */ /* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { |