diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2013-11-12 21:59:10 +0100 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-11-13 00:38:45 +0100 |
| commit | d8cfd23f6ab37ae68366625e144136392384638f (patch) | |
| tree | c2ce69e57c35dad907d78d84d4eaf8a1063327c8 /src/cpu/intel/model_2065x/Makefile.inc | |
| parent | c5e947ef17d98722d27a67d65a84a28fd5861dbd (diff) | |
| download | coreboot-d8cfd23f6ab37ae68366625e144136392384638f.tar.xz | |
intel/2065x: Use TSC for udelay()
For the ram init of Intel Nehalem ram init we need a udelay implementation.
Use common TSC framework for it as Intel Haswell already does.
Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4043
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/cpu/intel/model_2065x/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/model_2065x/Makefile.inc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 963fb1b3e3..3b3fc4e016 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -3,10 +3,16 @@ subdirs-y += ../../x86/name subdirs-y += ../../x86/cache subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/tsc subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../../x86/smm + +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c + ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c |