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authorFurquan Shaikh <furquan@google.com>2014-04-22 10:41:05 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2014-04-26 13:27:09 +0200
commit20f25dd5c8a513ee136e9f6d8c67959591298617 (patch)
treee42f5cfe77fb4f73d3b8eb759f5faa328997efc8 /src/cpu/intel/model_2065x
parent817149643c27fca022cf526d6113a4aff898d511 (diff)
downloadcoreboot-20f25dd5c8a513ee136e9f6d8c67959591298617.tar.xz
Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide consistency with other stage names (bootblock, romstage) and to allow any Makefile rule generalization, required for patches to be submitted later. Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/intel/model_2065x')
-rw-r--r--src/cpu/intel/model_2065x/cache_as_ram.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index b791881d69..e46a2ee3f3 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -227,7 +227,7 @@ before_romstage:
post_code(0x38)
/* Enable Write Back and Speculative Reads for the first MB
- * and coreboot_ram.
+ * and ramstage.
*/
movl $MTRRphysBase_MSR(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax