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| author | Aaron Durbin <adurbin@chromium.org> | 2016-03-07 16:23:47 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-03-08 23:58:01 +0100 |
| commit | 2a08137feebaf0f8f55feeff00096f5a9d03f44c (patch) | |
| tree | 269676f6d212e7d02d4069891d629881ccb7b034 /src/cpu/intel/model_2065x | |
| parent | f5452085979d9031023b1b810abf0493757e6287 (diff) | |
| download | coreboot-2a08137feebaf0f8f55feeff00096f5a9d03f44c.tar.xz | |
x86 chipsets: utilize x86_setup_mtrrs_with_detect()
For all the chipsets which were performing the following sequence:
x86_setup_fixed_mtrrs();
x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
Replace that with x86_setup_mtrrs_with_detect() since it is equivalent.
Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13936
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/cpu/intel/model_2065x')
| -rw-r--r-- | src/cpu/intel/model_2065x/model_2065x_init.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d7248422b7..4005b3d07c 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -358,7 +358,6 @@ static void intel_cores_init(struct device *cpu) static void model_2065x_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -374,9 +373,7 @@ static void model_2065x_init(struct device *cpu) printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid (), boot_cpu ()); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ |