diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-20 13:29:59 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 05:40:13 +0200 |
| commit | 8a2f167e7b99c171161937f52ccf5bc4ac9d6685 (patch) | |
| tree | d45b1c4f1060774fb7c4ed2b28f7ba6c1b3deae8 /src/cpu/intel/model_2065x | |
| parent | eb61ea84f7226d6c081441bbb6fbafbb920505db (diff) | |
| download | coreboot-8a2f167e7b99c171161937f52ccf5bc4ac9d6685.tar.xz | |
intel car: Unify postcodes
Not all are matched, but this makes it easier to backport
MTRR changes from haswell.
Change-Id: Ida5943b1469fc0089a31ff3b18131fb82b0941c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_2065x')
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 093c78457d..29ff01a26a 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -150,8 +150,6 @@ clear_var_mtrrs: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr - post_code(0x27) - post_code(0x28) /* Enable cache. */ movl %cr0, %eax @@ -177,8 +175,6 @@ before_romstage: */ movl %eax, %ebx - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -194,7 +190,7 @@ before_romstage: andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x31) + post_code(0x32) /* Disable the no eviction run state */ movl $NoEvictMod_MSR, %ecx |