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authorArthur Heymans <arthur@aheymans.xyz>2019-10-10 15:50:04 +0200
committerNico Huber <nico.h@gmx.de>2019-10-13 12:46:18 +0000
commit2882253237f254d5f78b7531ef3cefb974cd4bbb (patch)
tree91216e1814cff2806f15c503155d3ad3446cc48e /src/cpu/intel/model_2065x
parentb9c9cd75e71edf2fb9b34c451e7ad74a5200de1d (diff)
downloadcoreboot-2882253237f254d5f78b7531ef3cefb974cd4bbb.tar.xz
nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
A few notable changes: - Microcode init is done in assembly during the CAR init. - The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size against which the romstage stack guards protected. - The romstage mainboard_lpc_init() hook is removed in favor of the existing bootblock_mainboard_early_init(). Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu/intel/model_2065x')
-rw-r--r--src/cpu/intel/model_2065x/Kconfig4
-rw-r--r--src/cpu/intel/model_2065x/Makefile.inc5
-rw-r--r--src/cpu/intel/model_2065x/bootblock.c64
3 files changed, 4 insertions, 69 deletions
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 897a3b4804..572751186e 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -23,10 +23,6 @@ config CPU_SPECIFIC_OPTIONS
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
-config BOOTBLOCK_CPU_INIT
- string
- default "cpu/intel/model_2065x/bootblock.c"
-
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index dde4234521..142842174e 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -15,7 +15,10 @@ smm-y += finalize.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+bootblock-y += ../car/non-evict/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+bootblock-y += ../../x86/early_reset.S
+
postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
deleted file mode 100644
index 399f5e0838..0000000000
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <arch/io.h>
-#include <halt.h>
-
-#include <cpu/intel/microcode/microcode.c>
-
-#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK)
-#include <southbridge/intel/ibexpeak/pch.h>
-#include "model_2065x.h"
-#else
-#error "CPU must be paired with Intel Ibex Peak southbridge"
-#endif
-
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
- unsigned int type)
-
-{
- /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
- /* FIXME: It only support 4G less range */
- msr_t basem, maskm;
- basem.lo = base | type;
- basem.hi = 0;
- wrmsr(MTRR_PHYS_BASE(reg), basem);
- maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
- msr_t msr;
-
- disable_cache();
- set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
- enable_cache();
-
- /* Enable Variable MTRRs */
- msr.hi = 0x00000000;
- msr.lo = 0x00000800;
- wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
-
-static void bootblock_cpu_init(void)
-{
- enable_rom_caching();
- intel_update_microcode_from_cbfs();
-}