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author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-04 00:09:50 +0200 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-05 21:10:25 +0200 |
commit | 5c55463f500528b69c47a06da22339fa85d70b7e (patch) | |
tree | d36dfe145f135afa5453f6dd4fdbb32f14be5ef5 /src/cpu/intel/model_206ax/finalize.c | |
parent | 00636b0daefc3c499990744226a0e1a316d71731 (diff) | |
download | coreboot-5c55463f500528b69c47a06da22339fa85d70b7e.tar.xz |
Add support for Intel Sandybridge CPU
Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/855
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_206ax/finalize.c')
-rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c new file mode 100644 index 0000000000..9de94c4948 --- /dev/null +++ b/src/cpu/intel/model_206ax/finalize.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include "model_206ax.h" + +static void msr_set_bit(unsigned reg, unsigned bit) +{ + msr_t msr = rdmsr(reg); + + if (bit < 32) { + if (msr.lo & (1 << bit)) + return; + msr.lo |= 1 << bit; + } else { + if (msr.hi & (1 << (bit - 32))) + return; + msr.hi |= 1 << (bit - 32); + } + + wrmsr(reg, msr); +} + +void intel_model_206ax_finalize_smm(void) +{ + msr_set_bit(IA32_FEATURE_CONTROL, 0); + msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + + /* Lock AES-NI only if supported */ + if (cpuid_ecx(1) & (1 << 25)) + msr_set_bit(MSR_FEATURE_CONFIG, 0); + + msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); + msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); + msr_set_bit(MSR_PKG_POWER_LIMIT, 63); + msr_set_bit(MSR_PP0_POWER_LIMIT, 31); + msr_set_bit(MSR_PP1_POWER_LIMIT, 31); + msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set_bit(MSR_LT_LOCK_MEMORY, 0); +} |