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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-07-16 12:19:00 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-26 20:32:45 +0200 |
| commit | 556321167f3a3b4f4b934d114aca759387fddfaa (patch) | |
| tree | 74546d2ae1d4d3c66b8b08efefa64c5558681b22 /src/cpu/intel/model_206ax | |
| parent | d6aca0b7b14780a03c83e283f940f56c474a77dd (diff) | |
| download | coreboot-556321167f3a3b4f4b934d114aca759387fddfaa.tar.xz | |
CPU: Add option to set TCC activation offset
The default TCC activation offset is 0, which means TCC
activation starts at Tj_max. For devices with limited
cooling ability it may be desired to lower TCC activation.
This adds an option that can be declared in the devicetree
to set the TCC activation to a non-zero value.
Enable tcc_offset=15 in devicetree.cb and build/boot
the BIOS and check that the value is set in the MSR:
> and $(shr $(rdmsr 0 0x1a2) 24) 0xf
0xf
Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1343
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_206ax')
| -rw-r--r-- | src/cpu/intel/model_206ax/chip.h | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax.h | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 26 |
3 files changed, 29 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 48e0c89c21..96b4c5d9a9 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -34,4 +34,6 @@ struct cpu_intel_model_206ax_config { int c1_acpower; /* ACPI C1 on AC Power */ int c2_acpower; /* ACPI C2 on AC Power */ int c3_acpower; /* ACPI C3 on AC Power */ + + int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index cdcc233ee6..a7ca04a690 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -34,6 +34,7 @@ #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 +#define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 70a655a6f0..2ad8012edf 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -37,6 +37,7 @@ #include <pc80/mc146818rtc.h> #include <usbdebug.h> #include "model_206ax.h" +#include "chip.h" /* * List of suported C-states in this processor @@ -312,6 +313,28 @@ static void configure_c_states(void) wrmsr(MSR_PP1_CURRENT_CONFIG, msr); } +static void configure_thermal_target(void) +{ + struct cpu_intel_model_206ax_config *conf; + device_t lapic; + msr_t msr; + + /* Find pointer to CPU configuration */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic || !lapic->chip_info) + return; + conf = lapic->chip_info; + + /* Set TCC activaiton offset if supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -454,6 +477,9 @@ static void model_206ax_init(device_t cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); + /* Thermal throttle activation offset */ + configure_thermal_target(); + /* Enable Direct Cache Access */ configure_dca_cap(); |