Use 3rdparty/intel-microcode

Instead of maintaining this in 3rdparty/blobs use the
3rdparty/intel-microcode which is maintained by Intel.

This allows for some finegrained control where family+model span
multiple targets.

Microcode updates present in
3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those
contain updates not present in the Intel repo. Those are presumably
early CPU samples that did not end up in products.

The following MCU are get a new revision:
old:
 sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552
 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528
 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288
 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312
 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728
 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384
 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336
 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304
 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280
 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304
 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432
 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328
 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328

new:
 sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552
 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504
 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288
 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336
 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728
 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408
 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360
 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328
 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304
 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328
 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456
 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352
 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352

Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index e1fa87989c..78a6283a5d 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -28,8 +28,8 @@ romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
 
 cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
 postcar-y += ../car/non-evict/exit_car.S