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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-02-10 22:21:39 -0600
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-16 21:02:30 +0100
commit033bb4bc8d620288ed82fe982a32f567060499b6 (patch)
treebba24a07d463455825363b54894da14a6ba07025 /src/cpu/intel/model_6dx
parent4f731f2eabc9ef2c381b71515a3b2ff203c8653e (diff)
downloadcoreboot-033bb4bc8d620288ed82fe982a32f567060499b6.tar.xz
acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/cpu/intel/model_6dx')
-rw-r--r--src/cpu/intel/model_6dx/acpi/cpu.asl20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/intel/model_6dx/acpi/cpu.asl b/src/cpu/intel/model_6dx/acpi/cpu.asl
index 8928c3823f..04438a227a 100644
--- a/src/cpu/intel/model_6dx/acpi/cpu.asl
+++ b/src/cpu/intel/model_6dx/acpi/cpu.asl
@@ -4,34 +4,34 @@ External(PDC1)
// Power notification
-External (\_PR_.CPU0, DeviceObj)
-External (\_PR_.CPU1, DeviceObj)
-External (\_PR_.CPU0._PPC)
-External (\_PR_.CPU1._PPC)
+External (\_PR_.CP00, DeviceObj)
+External (\_PR_.CP01, DeviceObj)
+External (\_PR_.CP00._PPC)
+External (\_PR_.CP01._PPC)
Method (PNOT)
{
If (MPEN) {
If(And(PDC0, 0x08)) {
- Notify (\_PR_.CPU0, 0x80) // _PPC
+ Notify (\_PR_.CP00, 0x80) // _PPC
If (And(PDC0, 0x10)) {
Sleep(100)
- Notify(\_PR_.CPU0, 0x81) // _CST
+ Notify(\_PR_.CP00, 0x81) // _CST
}
}
If(And(PDC1, 0x08)) {
- Notify (\_PR_.CPU1, 0x80) // _PPC
+ Notify (\_PR_.CP01, 0x80) // _PPC
If (And(PDC1, 0x10)) {
Sleep(100)
- Notify(\_PR_.CPU1, 0x81) // _CST
+ Notify(\_PR_.CP01, 0x81) // _CST
}
}
} Else { // UP
- Notify (\_PR_.CPU0, 0x80)
+ Notify (\_PR_.CP00, 0x80)
Sleep(0x64)
- Notify(\_PR_.CPU0, 0x81)
+ Notify(\_PR_.CP00, 0x81)
}
}