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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-02-22 06:09:43 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-02-22 06:09:43 +0000 |
| commit | de3206a7bebce99f11e753164cc4d46357bba96a (patch) | |
| tree | 9843d883940e372dd357b1357ecd7eaba3e3365f /src/cpu/intel/model_6ex/cache_as_ram_disable.c | |
| parent | d650e9934ff8da9b9cb69e42e642c0ee6d390bf6 (diff) | |
| download | coreboot-de3206a7bebce99f11e753164cc4d46357bba96a.tar.xz | |
This is a general cleanup patch
- drop include/part and move files to include/
- get rid lots of warnings
- make resource allocator happy with w83627thg
- trivial cbmem resume fix
- fix payload and log level settings in abuild
- fix kontron mptable for virtual wire mode
- drop some dead includes and dead code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6ex/cache_as_ram_disable.c')
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram_disable.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c index fcdd3f2e19..6dac367c4d 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c @@ -54,8 +54,7 @@ void stage1_main(unsigned long bist) real_main(bist); /* No servicable parts below this line .. */ - -#if CAR_DEBUG +#ifdef CAR_DEBUG /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ unsigned v_esp; __asm__ volatile ( |