diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
| commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
| tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/cpu/intel/model_6ex | |
| parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) | |
| download | coreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz | |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6ex')
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 16 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/model_6ex_init.c | 8 |
2 files changed, 12 insertions, 12 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index d4f5d8bf5e..623b0a30a1 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -1,18 +1,18 @@ -/* +/* * This file is part of the coreboot project. - * + * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2007-2008 coresystems GmbH - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA @@ -206,7 +206,7 @@ clear_mtrrs: xorl %eax, %eax movl $((1024*1024) / 4), %ecx rep stosl - + post_code(0x37) #endif @@ -254,7 +254,7 @@ clear_mtrrs: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -262,7 +262,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index f879f34869..4f1d2043b6 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -204,7 +204,7 @@ static void model_6ex_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif |