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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 12:57:42 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-03 10:18:14 +0000 |
| commit | cf3076eff17dc9c152fca6ec9012e7734ff88b4c (patch) | |
| tree | ca4fd543bd87f02b3ff0e001ceca30c9c94c2f03 /src/cpu/intel/model_6ex | |
| parent | 6af3e6f4ff2ff727fec3034ef64c6dd604d44c9c (diff) | |
| download | coreboot-cf3076eff17dc9c152fca6ec9012e7734ff88b4c.tar.xz | |
nb/intel/i945: Use common SMM_TSEG code
Use the common SMM_TSEG code to relocate the smihandler to TSEG.
This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.
This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel d945gclf and Lenovo Thinkpad X60.
Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_6ex')
| -rw-r--r-- | src/cpu/intel/model_6ex/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 4321f2a5f5..13e08f0ed5 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name subdirs-y += ../common +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin |