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| author | Stefan Reinauer <stepan@coreboot.org> | 2010-12-11 22:14:44 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-12-11 22:14:44 +0000 |
| commit | 2a27b20226a2fd593bfd5f6a0eee45418233fe04 (patch) | |
| tree | 950aa542d9266c1cb004d2346062609c37ed16b3 /src/cpu/intel/model_6ex | |
| parent | 2b9070a610132eaf61dca67e7713c082903fffef (diff) | |
| download | coreboot-2a27b20226a2fd593bfd5f6a0eee45418233fe04.tar.xz | |
factor out cpu power management base into a separate file. And fix a bug in
model_1067x
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6ex')
| -rw-r--r-- | src/cpu/intel/model_6ex/model_6ex_init.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 384b2bf68b..eee651a207 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -29,6 +29,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -80,15 +81,6 @@ static void enable_vmx(void) #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -/* MWAIT coordination I/O base address. This must match - * the \_PR_.CPU0 PM base address. - */ -#define PMB0_BASE 0x510 - -/* PMB1: I/O port that triggers SMI once cores are in the same state. - * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] - */ -#define PMB1_BASE 0x800 #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { |