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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-01 08:47:51 +0200
committerMartin Roth <martinroth@google.com>2018-10-11 21:06:53 +0000
commit419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 (patch)
tree8b5a5413e791e15d7e386c958b2a24899d8cddc2 /src/cpu/intel/model_6ex
parent603963e1ba4147ef31a72b94304708ab416e3b6a (diff)
downloadcoreboot-419bfbc1f1e7bb40c1e5698e1f50d4e275665d97.tar.xz
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/model_6ex_init.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 68be5679c8..5041dcd51d 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -58,7 +58,6 @@ static void configure_c_states(void)
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}
-#define IA32_MISC_ENABLE 0x1a0
static void configure_misc(void)
{
msr_t msr;