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| author | Rudolf Marek <r.marek@assembler.cz> | 2011-10-30 18:06:58 +0100 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2011-10-30 21:28:11 +0100 |
| commit | 9438da370fb66292babf5a2f621a67fd4b3699de (patch) | |
| tree | d6b1bd075a147f18c87b5a74cffe5e6fe20ec4d2 /src/cpu/intel/model_6ex | |
| parent | af3dce981db63eb16d127347264a46247ed893bb (diff) | |
| download | coreboot-9438da370fb66292babf5a2f621a67fd4b3699de.tar.xz | |
Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
It is meant to be a address and not a dereference. Otherwise MTRR
is filled with code and not with the address.
This is what I hate at most on the AT&T syntax. Instead of taking
the address, it was a dereference. Not greatly visible, except
I wondered why opcode is not 0xb4 but 0xa1 and it took another
half an our to see it.
Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel/model_6ex')
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index fa35fc9994..3a12cf6dd3 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -106,7 +106,7 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %eax + movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr |