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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-12-06 23:14:54 -0600
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-01-16 05:34:25 +0100
commit2c38f50b4ad8850676a70427bf1e2e9e9aab82a4 (patch)
tree68fe15f5e270e69ab9810b12fa2bf61d7ff71585 /src/cpu/intel/model_6ex
parentb4c39902edbba61827c60a75fe84e748e217b8be (diff)
downloadcoreboot-2c38f50b4ad8850676a70427bf1e2e9e9aab82a4.tar.xz
cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all Intel CPUs. The same function is used to inject the update in both CBFS and hardcoded cases, and in both of these cases, the microcode resides in the ROM. This should be a safe change across the board. The function which loaded compiled-in microcode is also removed here in order to prevent it from being used in the future. The dummy terminators from microcode need to be removed if this change is to work when generating microcode from several microcode_blob.c files, as is the case for older socketed CPUs. Removal of dummy terminators is done in a subsequent patch. Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4495 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/Kconfig1
-rw-r--r--src/cpu/intel/model_6ex/Makefile.inc1
-rw-r--r--src/cpu/intel/model_6ex/microcode_blob.c10
-rw-r--r--src/cpu/intel/model_6ex/model_6ex_init.c12
4 files changed, 13 insertions, 11 deletions
diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig
index e2b1986132..8187838163 100644
--- a/src/cpu/intel/model_6ex/Kconfig
+++ b/src/cpu/intel/model_6ex/Kconfig
@@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6EX
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index b515c4f69a..6d943023c8 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,3 +1,4 @@
ramstage-y += model_6ex_init.c
subdirs-y += ../../x86/name
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
new file mode 100644
index 0000000000..0798316d40
--- /dev/null
+++ b/src/cpu/intel/model_6ex/microcode_blob.c
@@ -0,0 +1,10 @@
+unsigned microcode_updates_6ex[] = {
+ #include "microcode-1624-m206e839.h"
+ #include "microcode-1729-m206ec54.h"
+ #include "microcode-1869-m806ec59.h"
+ /* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index e9c63da16f..4dc642a61e 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -33,16 +33,6 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
-static const uint32_t microcode_updates[] = {
- #include "microcode-1624-m206e839.h"
- #include "microcode-1729-m206ec54.h"
- #include "microcode-1869-m806ec59.h"
- /* Dummy terminator */
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
-};
#define IA32_FEATURE_CONTROL 0x003a
@@ -160,7 +150,7 @@ static void model_6ex_init(device_t cpu)
x86_enable_cache();
/* Update the microcode */
- intel_update_microcode(microcode_updates);
+ intel_update_microcode_from_cbfs();
/* Print processor name */
fill_processor_name(processor_name);