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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-06 11:41:09 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 23:25:53 +0200
commit8ee04d784cbaeb8a30276ac22aa99ddda44092b7 (patch)
tree209414bf6d307b8bb9cbe8816447ee4a79e81c06 /src/cpu/intel/model_6ex
parent41c10cd2d73198e61573af1341d5826654f1133a (diff)
downloadcoreboot-8ee04d784cbaeb8a30276ac22aa99ddda44092b7.tar.xz
usbdebug: Put ehci_debug_info in CAR_GLOBAL
Store EHCI Debug Port runtime variables in CAR_GLOBAL. For platforms without CAR_MIGRATION, logging on EHCI Debug Port is temporarily lost when CAR is torn down at end of romstage. On model_2065x and model_206ax ehci_debug_info was overlapping the MRC variable region and additionally migration used incorrect size for the structure. Change-Id: I5e6c613b8a4b1dda43d5b69bd437753108760fca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3475 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 50fab35ccc..ac3c66b734 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -126,12 +126,7 @@ clear_mtrrs:
movl %eax, %cr0
/* Set up the stack pointer. */
-#if CONFIG_USBDEBUG
- /* Leave some space for the struct ehci_debug_info. */
- movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
-#else
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
-#endif
movl %eax, %esp
/* Restore the BIST result. */