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authorStefan Reinauer <stepan@coresystems.de>2009-10-26 16:49:16 +0000
committerStefan Reinauer <stepan@openbios.org>2009-10-26 16:49:16 +0000
commita769344d437d608a2e714a01cdb847a2a69d0826 (patch)
tree9905d1764d3c5358c399c94c4c18b884068ade5a /src/cpu/intel/model_6ex
parentfbb8a015436d745916bfde6b521b3c36ae534e5e (diff)
downloadcoreboot-a769344d437d608a2e714a01cdb847a2a69d0826.tar.xz
intel core and core 2:
- small preprocessor fix - leave some space in the CAR area for the usbdebug structure if usbdebug is used Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index ee175affed..9623dc4086 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -94,7 +94,6 @@ clear_mtrrs:
//movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
-#endif
/* Enable Cache As RAM mode by disabling cache */
movl %cr0, %eax
@@ -117,10 +116,16 @@ clear_mtrrs:
/* enable cache */
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
- movl %eax, %cr0
+ movl %eax, %cr0
+#endif
/* Set up stack pointer */
+#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
+ /* leave some space for the struct ehci_debug_info */
+ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
+#else
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+#endif
movl %eax, %esp
/* Restore the BIST result */