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authorStefan Reinauer <stefan.reinauer@coreboot.org>2011-04-21 20:45:45 +0000
committerStefan Reinauer <stepan@openbios.org>2011-04-21 20:45:45 +0000
commitd4814bd41c080fb9dda87c762fcaecf4e72fc996 (patch)
tree57a44f8cbfad3642084b8e3d092e230b8f7e7198 /src/cpu/intel/model_6ex
parent1d888a97849d68a7136da558c3697c7f2a8d898a (diff)
downloadcoreboot-d4814bd41c080fb9dda87c762fcaecf4e72fc996.tar.xz
more ifdef -> if fixes
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 0ee26fcdd2..0906bc0e5f 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -102,7 +102,7 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#if CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
@@ -128,7 +128,7 @@ clear_mtrrs:
movl %eax, %cr0
/* Set up the stack pointer. */
-#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
+#if CONFIG_USBDEBUG
/* Leave some space for the struct ehci_debug_info. */
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
#else