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authorStefan Reinauer <stefan.reinauer@coreboot.org>2011-04-14 20:06:30 +0000
committerStefan Reinauer <stepan@openbios.org>2011-04-14 20:06:30 +0000
commit139e6f9555d6ff31c81ff6620bbe6214fa11b1e5 (patch)
tree6ff72344e33b5d04c4f33f33b7121cf0e9fba225 /src/cpu/intel/model_6ex
parent528b43db32647c10d2d6b16b3585547bf3ab7b03 (diff)
downloadcoreboot-139e6f9555d6ff31c81ff6620bbe6214fa11b1e5.tar.xz
Use symbolic names for some MTRR bits instead of numbers in CAR code
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index fc4947600f..0ee26fcdd2 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -63,14 +63,14 @@ clear_mtrrs:
/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx
wrmsr
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- orl $(1 << 11), %eax
+ orl $MTRRdefTypeEn, %eax
wrmsr
/* Enable L2 cache. */
@@ -118,7 +118,7 @@ clear_mtrrs:
movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
@@ -160,7 +160,7 @@ clear_mtrrs:
/* Disable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- andl $(~(1 << 11)), %eax
+ andl $(~MTRRdefTypeEn), %eax
wrmsr
post_code(0x31)
@@ -201,7 +201,7 @@ clear_mtrrs:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+ movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx // 36bit address space
wrmsr
@@ -217,7 +217,7 @@ clear_mtrrs:
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- orl $(1 << 11), %eax
+ orl $MTRRdefTypeEn, %eax
wrmsr
post_code(0x3b)